1. Field of the Invention
The present invention relates to a semiconductor storage device, and in particular, to a semiconductor storage device with a structure where memory cell arrays are laminated on the semiconductor substrate.
2. Description of the Related Art
Resistive memory has attracted increased attention as a likely candidate for replacing flash memory. As described herein, it is assumed that the resistive memory devices include Resistive RAM (ReRAM), in a narrow sense, that uses a transition metal oxide as a recording layer and stores its resistance states in a non-volatile manner, as well as Phase Change RAM (PCRAM) that uses chalcogenide, etc., as a recording layer to utilize the resistance information of crystalline states (conductors) and amorphous states (insulators).
It is known that the variable resistance elements in resistive memory have two modes of operation. One is to set a high resistance state and a low resistance state by switching the polarity of the applied voltage, which is referred to as “bipolar type”. The other enables the setting of a high resistance state and a low resistance state by controlling the voltage values and the voltage application time, without switching the polarity of the applied voltage, which is referred to as “unipolar type”.
To achieve high-density memory cell arrays, the unipolar type is preferable. This is because that the unipolar type solution enables, without transistors, cell arrays to be configured by superposing variable resistance elements and rectifier elements, such as diodes, on respective intersections between bit lines and word lines. Moreover, large capacity may be achieved without an increase in cell array area by arranging such memory cell arrays laminated in a three-dimensional manner (see, Japanese Unexamined Patent Publication No. (Kohyo) 2005-522045).
Performing setting operation for writing data to, reset operation for erasing data from, and read operation to reading data from a memory cell array provided on the semiconductor substrate involves a certain amount of processing time. To improve the processing speed of the resistive memory device during the set, reset, and read operations, a larger number of memory cells need to be operated at the same time in the corresponding memory cell array. However, as the number of memory cells operated at the same time increases, a larger voltage drop is caused due to the parasitic resistance of wirings in the memory cell array. This voltage drop may prevent a sufficient voltage/current from being applied to the memory cell, which could result in failure of operations to be performed on a desired memory cell.